Ripple Carry Adder (리플 캐리 가산기), n bit full adder 설계

 

Ripple Carry Adder 개념 및 구조도

 

 

4 bit Ripple Carry Adder 설계

module ripple_carry_adder_4bit(
    input   wire    [3:0]   a, b,
    input   wire            c_in,
    output  wire    [3:0]   sum,
    output  wire            c_out
);
    wire c1, c2, c3;
    
    // 4_bit ripple carry adder body
    // instantiate full_adder_Structure
    full_adder fa_1 (a[0], b[0], c_in, sum[0], c1);
    full_adder fa_2 (a[1], b[1], c1,   sum[1], c2);
    full_adder fa_3 (a[2], b[2], c2,   sum[2], c3);
    full_adder fa_4 (a[3], b[3], c3,   sum[3], c_out); 

endmodule

 

Ripple Carry Adder RTL Schematic

4 bit Ripple Carry adder Simulation Waveform

 

 

 

4 bit Full adder 설계

module four_bit_adder (
    input   wire    [3:0]   x, y,
    input   wire            c_in,
    output  wire    [3:0]   sum,
    output  wire            c_out
); 
    wire c1, c2, c3; // intermediate carries 
    
    // four_bit adder body (Structure)
    full_adder fa_st_1 (x[0], y[0], c_in, sum[0], c1);
    full_adder fa_st_2 (x[1], y[1], c1,   sum[1], c2);
    full_adder fa_st_3 (x[2], y[2], c2,   sum[2], c3);
    full_adder fa_st_4 (x[3], y[3], c3,   sum[3], c_out); 
    
endmodule

 

4 bit Full Adder Simulation Waveform

 

 

4-bit full adder Structural RTL Schematic

4-bit full adder Dataflow RTL Schematic

4-bit full adder Behavioral RTL Schematic

 

 

 

 

 

 

 

N bit full adder

 

module adder_nbit_parameter #(
    parameter N = 4  // set default value 
)(
    input  wire     [N-1:0]     x, 
    input  wire     [N-1:0]     y,
    input  wire                 c_in,
    
    output wire     [N-1:0]     sum,
    output wire                 c_out
);
   assign {c_out, sum} = x + y + c_in; 
endmodule

 

parameter = 4 설정 시 RTL Schematic

Simulation Waveform